www.siliconstandard.com 1 of 5 complementary n- and p-channel enhancement-mode power mosfets simple drive requirement lower gate charge fast switching characteristic description advanced power mosfets from silicon standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the s s m4565m is in the so-8 package, which is widely preferred for commercial a nd industrial surface mount applications , and is we ll suited for low voltage applications such as dc/dc converters. this device is available with pb-free lead finish (second-level interconnect) as SSM4565GM. ssm 4565 m/gm 12/10/2004 rev.2.01 n-ch bv dss 40v r ds(on) 25mw i d 7.6a p-ch bv dss -40v r ds(on) 33mw i d -6.5a absolute maximum ratings symbol parameter rating units n-channel p-channel v ds drain-source voltage 40 -40 v v gs gate-source voltage 20 20 v i d @ t a =25c continuous drain current 3 7.6 -6.5 a i d @ t a =70c continuous drain current 3 6 -5.2 a i dm pulsed drain current 1 30 -30 a p d @ t a =25c total power dissipation 2.0 w linear derating factor 0.016 w/c t stg storage temperature range -55 to 150 c t j operating junction temperature range -55 to 150 c symbol value unit rthj-a thermal resistance junction-ambient 3 max. 62.5 c/w parameter thermal data s1 g1 s2 g2 d1 d1 d2 g2 d2 s2 g1 d1 s1 s1 g1 s2 g2 d1 d1 d2 d2 so-8 www..net
www.siliconstandard.com 2 of 5 ssm4565m/gm 12/10/2004 rev.2.01 n-channel electrical characteristics @ t j =25 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 40 - - v d bv dss / d t j breakdown voltage temperature coefficient reference to 25c, i d =1ma - 0.03 - v/c r ds(on) static drain-source on-resistance 2 v gs =10v, i d =7a - - 25 mw v gs =4.5v, i d =5a - - 32 mw v gs(th) gate threshold voltage v ds =v gs , i d =250ua 1 - 3 v g fs forward transconductance v ds =10v, i d =7a - 12 - s i dss drain-source leakage current (t j =25 o c) v ds =40v, v gs =0v - - 1 ua drain-source leakage current (t j =70 o c) v ds =32v, v gs =0v - - 25 ua i gss gate-source leakage v gs =20v - - na q g total gate charge 2 i d =7a - 17 27 nc q gs gate-source charge v ds =32v - 4 - nc q gd gate-drain ("miller") charge v gs =4.5v - 10 - nc t d(on) turn-on delay time 2 v ds =20v - 11 - ns t r rise time i d =1a - 8 - ns t d(off) turn-off delay time r g =3.3w , v gs =10v - 30 - ns t f fall time r d =20w - 11 - ns c iss input capacitance v gs =0v - 1400 2240 pf c oss output capacitance v ds =25v - 250 - pf c rss reverse transfer capacitance f=1.0mhz - 170 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =1.7a, v gs =0v - - 1.2 v t rr reverse recovery time 2 i s =7a, v gs =0v - 26 - ns q rr reverse recovery charge di/dt=100a/s - 21 - nc 100 www..net
www.siliconstandard.com 3 of 5 ssm 4565 m/gm 12/10/2004 rev.2.01 p-channel electrical characteristics @ t j =25 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =-250ua -40 - - v d bv dss /d t j breakdown voltage temperature coefficient reference to 25c, i d =-1ma - -0.03 - v/c r ds(on) static drain-source on-resistance 2 v gs =-10v, i d =-6a - - 33 mw v gs =-4.5v, i d =-4a - - 42 mw v gs(th) gate threshold voltage v ds =v gs , i d =-250ua -1 - -3 v g fs forward transconductance v ds =-10v, i d =-6a - 10 - s i dss drain-source leakage current (t j =25 o c) v ds =-40v, v gs =0v - - -1 ua drain-source leakage current (t j =70 o c) v ds =-32v, v gs =0v - - -25 ua i gss gate-source leakage v gs =20v - - na q g total gate charge 2 i d =-6a - 20 32 nc q gs gate-source charge v ds =-32v - 4 - nc q gd gate-drain ("miller") charge v gs =-4.5v - 10 - nc t d(on) turn-on delay time 2 v ds =-20v - 11 - ns t r rise time i d =-1a - 7 - ns t d(off) turn-off delay time r g =3.3w , v gs =-10v - 67 - ns t f fall time r d =20w -43- ns c iss input capacitance v gs =0v - 1440 2300 pf c oss output capacitance v ds =-25v - 250 - pf c rss reverse transfer capacitance f=1.0mhz - 190 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =-1.7a, v gs =0v - - -1.2 v t rr reverse recovery time 2 i s =-6a, v gs =0v - 27 - ns q rr reverse recovery charge di/dt=-100a/s - 23 - nc notes: 1.pulse width limited by max. junction temperature. 2.pulse width < 300us , duty cycle < 2%. 3.surface mounted on 1 in 2 copper pad of fr4 board ; 135c/w when mounted on min. copper pad. 100 www..net
www.siliconstandard.com 4 of 5 ssm 4565 m/gm 12/10/2004 rev.2.01 n-channel fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0 20 40 60 80 100 120 140 0123456 v ds , drain-to-source voltage (v) i d , drain current (a) t a =25 o c 10v 7.0v 5.0v 4.5v v g =3.0v 0 20 40 60 80 100 120 0123456 v ds , drain-to-source voltage (v) i d , drain current (a) t a = 150 o c 10v 7.0v 5.0v 4.5v v g =3.0v 15 19 23 27 35791 1 v gs , gate-to-source voltage (v) r ds(on) (m w ) i d =5a t a =25 o c 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =7a v g =10v 0 2 4 6 8 0 0.2 0.4 0.6 0.8 1 1.2 v sd , source-to-drain voltage (v) i s (a) t j =25 o c t j =150 o c 0.5 0.7 0.9 1.1 1.3 1.5 -50 0 50 100 150 t j , junction temperature ( o c) normalized v gs(th) (v) www..net
www.siliconstandard.com 4 of 5 ssm 4565 m/gm 12/10/2004 rev.2.01 n-channel fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fi g 10. effective transient thermal im p edanc e fig 11. switching time waveform fig 12. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 4.5v q gs q gd q g charge 0 2 4 6 8 10 12 14 0 1 02 03 04 0 q g , total gate charge (nc) v gs , gate to source voltage (v) i d =7a v ds =32v 100 1000 10000 1 5 9 1 31 72 12 52 9 v ds , drain-to-source voltage (v) c (pf) f =1.0mhz c iss c oss c rss 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-to-source voltage (v) i d (a) t a =25 o c single pulse 100us 1ms 10ms 100ms 1s dc 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) p dm duty factor = t/t peak t j = p dm x r thja + t a r thja =135 o c/w t t 0.02 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse www..net
www.siliconstandard.com 5 of 5 ssm 4565 m/gm 12/10/2004 rev.2.01 p-channel 0 20 40 60 80 100 0123456789 -v ds , drain-to-source voltage (v) -i d , drain current (a) t a =25 o c -10v -7.0v -5.0v -4.5v v g =-3.0v 0 20 40 60 80 100 0123456789 -v ds , drain-to-source voltage (v) -i d , drain current (a) t a = 150 o c -10v -7.0v -5.0v -4.5v v g =-3.0v fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 25 29 33 37 41 35791 1 -v gs ,gate-to-source voltage (v) r ds(on) (m w ) i d =-4a t a =25 o c 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =-6a v g =-10v 0 1 2 3 4 5 6 0 0.2 0.4 0.6 0.8 1 1.2 -v sd , source-to-drain voltage (v) -i s (a) t j =25 o c t j =150 o c 0.0 0.5 1.0 1.5 2.0 -50 0 50 100 150 t j , junction temperature ( o c) normalized -v gs(th) (v) www..net
www.siliconstandard.com 4 of 5 ssm 4565 m/gm 12/10/2004 rev.2.01 p-channel fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g -4.5v q gs q gd q g charge 0 4 8 12 16 0.0 10.0 20.0 30.0 40.0 50.0 q g , total gate charge (nc) -v gs , gate to source voltage (v) i d =-6a v ds =-32v 100 1000 10000 1 5 9 13 17 21 25 29 -v ds , drain-to-source voltage (v) c (pf) f =1.0mhz c iss c oss c rss 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-to-source voltage (v) -i d (a) t a =25 o c single pulse 100us 1ms 10ms 100ms 1s dc 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) p dm duty factor = t/t peak t j = p dm x r thja + t a r thja =135 o c/w t t 0.02 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse www..net
in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 5 of 5 ssm 4565 m/gm 12/10/2004 rev.2.01 www..net
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